else if (( DEPTH == 4096) & (DATA_W == 72)) begin: gen_sram_2048w_36b_4096_72
  logic [10:0] addr_temp;
  logic [71:0] wdata_temp;
  logic [71:0] bweb_temp;
  logic [71:0] rdata_temp[1:0];
  logic [1:0] web_temp;
  logic [1:0] ceb_temp;
  logic       read_en;
  logic       addr_top_q;

  assign addr_temp  = addr[10:0];
  assign wdata_temp = wdata;
  assign bweb_temp  = ~wen;
  assign read_en    = cs & ~wr;
  always @(posedge clk)
  if (read_en)
    addr_top_q <= addr[11];

  assign rdata = 
        (addr_top_q == 1'b1) ? rdata_temp[1] :
                               rdata_temp[0];

  for (genvar i=0; i<2; i++) begin: gen_sram_2048w_36b_4096_72_subblock
    assign  web_temp[i] = ~(wr & (addr[11]==i[0]));  
    assign  ceb_temp[i] = ~(cs & (addr[11]==i[0]));
    TEM5N28HPCPLVTA2048X36M8SWSO sram_0
      (.SLP  (1'b0),
      .SD   (1'b0),
      .A    (addr_temp),
      .D    (wdata_temp[35:0]),
      .BWEB (bweb_temp[35:0]),
      .Q    (rdata_temp[i][35:0]),
      .WEB  (web_temp[i]),
      .CEB  (ceb_temp[i]),
      .CLK  (clk)
    );
    TEM5N28HPCPLVTA2048X36M8SWSO sram_1
      (.SLP  (1'b0),
      .SD   (1'b0),
      .A    (addr_temp),
      .D    (wdata_temp[71:36]),
      .BWEB (bweb_temp[71:36]),
      .Q    (rdata_temp[i][71:36]),
      .WEB  (web_temp[i]),
      .CEB  (ceb_temp[i]),
      .CLK  (clk)
    );
  end
  end
